Lessons

• Lesson 0: Setup and the ASIC design flow
• Lesson 1: Introduction to Verilog
• Lesson 2: Synthesis
• Lesson 3: Place and route
• Lesson 4: Gate level simulation
• Lesson 5: Estimating timing and power
• Lesson 6: SoC design and interconnects
• Lesson 7: Design for test

Tool Guides

• Synopsys Reference Design Methodology
• Synopsys VCS
• Synopsys DC
• Synopsys ICC
• Synopsys PrimeTime

More Resources

• Plug Synopsys office hours
• Link to userguides
• Link to ece5745